Field of the Invention
The present invention generally relates to “Solid State Drives” (hereinafter, SSD devices), such as SSD devices provided with non-volatile memory chips (e.g., NAND flash memory chips) for storing bits. More particularly, the present invention relates to SSD devices provided with error correction capabilities. Even more particularly, the present invention relates to a method for decoding bits in such SSD devices, and to SSD devices (or controllers thereof) implementing the method.
Overview of the Related Art
SSD devices are nowadays widely used, for example as storage units of computers in replacement of HDD (“Hard Disk Drives”).
A common SSD device comprises non-volatile memory chips (for example, NAND flash memory chips) each one comprising non-volatile memory cells for storing data (bits) even in the absence of external power supply, and a SSD device controller (hereinafter, SSD controller) for managing SSD device operations, such as write/program, erase and read operations.
Each memory cell comprises a floating gate transistor. Each bit or group of bits (identifying a respective logical state of the memory cell) is physically stored in each memory cell in the form of electric charge in the floating gate, which defines a corresponding threshold voltage of the transistor. The number of bits each memory cell is capable of storing depends on memory cell technology. For example, in “Single-Level Cell” (SLC) technology each memory cell (or SLC memory cell) is capable of storing one symbol (or bit pattern) comprising one bit (i.e. two logical states, 0 or 1, defining two threshold voltages), in “Multi-Level Cell” (MLC) technology each memory cell (or MLC memory cell) is capable of storing one symbol comprising more than one bit, typically two bits (i.e. four logical states, 00, 01, 10, or 11, defining four threshold voltages), whereas in “Tri-Level Cell” technology each memory cell (or TLC memory cell) is capable of storing one symbol comprising three bits (i.e. eight logical states, 000, 001, 010, 011, 100, 101, 110 or 111, defining eight threshold voltages).
While, ideally, all memory cells in a memory chip should feature same (nominal) threshold voltages for same logical states (or, equivalently, for same symbols), practically each threshold voltage associated with a corresponding logical state (or, equivalently, with a corresponding symbol) differs across the memory cells and defines a respective threshold voltage distribution (typically, a Gaussian-type probability distribution), thus resulting in a number of threshold voltage distributions equal to the possible logical states each memory cell can take.
Ideally, the threshold voltage distributions are spaced apart from one another, and a corresponding reference voltage is set between each pair of adjacent threshold voltage distributions for sensing/reading the logical state of the memory cells. This is schematically shown in the top drawing of FIG. 2B for a 2-bit MLC memory cell (hereinafter referred to as MLC memory cell for the sake of conciseness) and in the top drawing of FIG. 2C for a TCL memory cell. In such figures the threshold voltage distributions are denoted by Dj (j ranging from 1 to 4 for the MLC memory cell and from 1 to 8 for the TLC memory cell).
As visible in these drawings, the threshold voltage distributions D3 are (ideally) spaced apart from one another, and a corresponding reference voltage Vk (usually referred to as hard reference voltage) is set between each pair of adjacent threshold voltage distributions Dj for sensing/reading the logical state of the memory cells (k=1, 2, 3 in the example of FIG. 2B and k=1, 2, 3, 4, 5, 6, 7 in the example of FIG. 2C).
In case of the MLC memory cell, during a read operation a threshold voltage below the hard reference voltage V1 represents the symbol “11”, a threshold voltage between the hard reference voltages V1 and V2 represents the symbol “01”, a threshold voltage between the hard reference voltages V2 and V3 represents the symbol “00”, and a threshold voltage above the hard reference voltage V3 represents the symbol “10”.
In case of the TLC memory cell, during a read operation, a threshold voltage below the hard reference voltage V1 represents the symbol “111”, a threshold voltage between the hard reference voltages V1 and V2 represents the symbol “011”, a threshold voltage between the hard reference voltages V2 and V3 represents the symbol “001”, a threshold voltage between the hard reference voltages V3 and V4 represents the symbol “101”, a threshold voltage between the hard reference voltages V4 and V5 represents the symbol “100”, a threshold voltage between the hard reference voltages V5 and V6 represents the symbol “000”, a threshold voltage between the hard reference voltages V6 and V7 represents the symbol “010”, and a threshold voltage above the hard reference voltage V7 represents the symbol “110”.
To read a memory cell, the threshold voltage of that memory cell (i.e., the threshold voltage to which that memory cell is responsive) is compared to the hard reference voltages Vk. Typically, reading a memory cell that stores a symbol of m bits requires, for at least one page of memory cells (hereinafter, memory page), m such comparisons.
For example, when m=3, such as in the TLC memory cell, the threshold voltage is first compared to the hard reference voltage V4. Depending on the outcome of that comparison, the threshold voltage is then compared either to the hard reference voltage V2 or to the hard reference voltage V6. Depending on the outcome of the second comparison, the threshold voltage is then compared either to the hard reference voltages V1 or V3 or to the hard reference voltages V5 or V7.
However, the increasing of the number of bits per memory cell causes, for a same threshold voltage distribution space (i.e., for the same allowed maximum and minimum threshold voltages), a higher number of threshold voltage distributions. A higher number of threshold voltage distributions in the same threshold voltage distribution space results in threshold voltage distributions that are closer to each other. This makes the memory cells more prone to suffer severe cell-to-cell interference and retention noise, which translates into partially overlapping areas of adjacent threshold voltage distributions Dj (shown in the bottom drawings of FIGS. 2B and 2C) and, hence, into the increasing of the number of bit errors.
In order to compensate for larger bit errors, and to increase SSD device reliability, “Forward Error Correction” has been proposed (and typically implemented in the SSD controller) for locating and correcting bit errors. According to “Forward Error Correction” principles, the bits to be stored are encoded in a redundant way (e.g., by adding parity bits) by means of an “Error Correction Code” (ECC code), so that redundancy allows detecting a limited number of bit errors that may occur anywhere in the read bits, and to correct these errors. Generally, the number of detectable and correctable bit errors increases as the number of parity bits in the ECC code increases.
The probability of corrupted read bits, which therefore contains incorrect bits, before correction is referred to as “Raw Bit Error Rate” (RBER). The RBER is typically estimated (e.g., by the SSD controller) according to a shape of the threshold voltage distributions Dj, and particularly according to the overlapping areas of the adjacent threshold voltage distributions Dj.
As a result of the advances in memory cell technology, the RBER for selected memory cells is increasingly nearing the Shannon limit of the communication channel. The RBER observed after application of the ECC code is referred to as “Frame Bit Error Rate” (FER), whereas the FER divided by the number of read bits is referred to as “Uncorrectable Bit Error Rate” (UBER).
The acceptable UBER is often dependent upon the application in which the SSD device is intended to be employed. In the case of price sensitive, consumer applications, which experience a relatively low number of accesses (e.g., program/erase cycles), the SSD device may tolerate a higher UBER as compared to a high-end application experiencing a relatively high number of accesses, such as an enterprise application.
To achieve an acceptable UBER, especially for enterprise applications, ECC codes such as “Low-Density Parity-Check” (LDPC) codes have been widely used (both alone and in combination with other ECC codes), which allow determining each bit value by means of hard bits (i.e., the read bits resulting from comparisons to the hard reference voltages Vk) and of additional information including soft bits and an indication of the reliability of each read soft bit typically evaluated according to RBER—the decoding based on the hard and soft bits being referred to as hard and soft decoding, respectively.
In the known solutions, the soft bits mainly arise from multiple read operations. Indeed, according to a common approach, when a read operation takes place on selected memory cells, and the number of bit errors is found to be higher than correction capabilities of the “Forward Error Correction”, the flash memory device (e.g., the SSD controller thereof) is typically configured to reread the selected memory cells at different values of the reference voltages to attempt to establish the bits in those areas of the threshold voltage distributions Dj wherein bit error is most likely. Such multiple readings are typically carried out by moving the hard reference voltages Vk in a neighborhood thereof, thus obtaining a number of additional reference voltages (or soft reference voltages) VkA-VkF associated with each hard reference voltage Vk (in the following the overall reference voltages including both the hard reference voltages Vk and the associated soft reference voltages VkA-VkF will be also denoted, as a whole, by reference voltages VkA, VkA-VkF for the sake of conciseness).